FinFET bosch etch tsv vmin SK하이닉스 leakage TSMC 경력 apcvd lpcvd oxide fixed charge denuded zone bulk micro defect 성균관대학교 반도체 설계 재직자 과정 gate last poly residue d0 defect density n factor dly 가속모델 tddb virtual gnd footer transistor pelgrom random dopant fluctuation local variation vt mismatch iddq ir drop static power short-circuit power dynamic power gate cut stuck-at interface trap parasitic capacitance rch pbti 티스토리챌린지 오블완 ceff low k DIBL GAAFET LDE MOSCAP Bose-Einstein FT-IR decap capacitance 3nm NBTI DFT sdb MISMATCH 7nm design rule Scattering skct defect overlap mim DRC spacer Qual junction Corner Loss poisson Weibull SRAM BMD Monte Carlo DDB Dz Mobility SAC LVS 특성 yield scan Gate FIN 서류 신뢰성 temperature 온도 RDF MoM extension RPG 면접